1. Field of the Invention
This invention relates to integrated circuit manufacturing processes, and more particularly relates to a composite stencil process for deposition of contacts to active devices, which composite stencil process is minimally susceptible to local geometry effects caused by the presence of lift-off stencil material proximate to active device areas.
2. Description of the Prior Art
The prior art of integrated circuit manufacture has passed from art to science in areas of purity of materials, miniaturization of circuit connectors and active devices so as to allow massive replication of circuits on a chip, and many other process improvements. As process improvements are made, demand absorbs these improvements as integration scale increases in number of devices per chip from 1 to 2, 4, 16, 64, 1024 . . . toward very large scale integration of millions of devices per chip. As these changes occur, new problems arise. One change is that vertical dimensional control has become vital; even thin films at high scales of integration can shadow adjacent device areas during deposition, and cause degradation of device performance unacceptable in very large scale integration.
Integrated circuits normally require contact and conductor metallization for interconnection to active device areas, such as semiconductor electrodes or Josephson junction electrodes. As integrated circuits become more complex, the need for crossovers and layer interconnections have required the development of improved manufacturing techniques to free the designer from the tyrannical demands of vertical topography. The milder demands of horizontal topography are generally not addressed.
Horizontal topography is just beginning to be recognized as a design constraint; as integration reaches levels where deposition shadowing can affect device parameters, horizontal topography becomes a serious design constraint. Proximity effects, which may result from the mere physical presence of one masking material adjacent to an area where another material is to be deposited or grown, have become a major problem area in the production of Josephson junction devices. The actual edge of a thin film might be the locus of an active device, and the thickness of the photoresist might be so great that its shadow might adversely affect the properties of the device defined by an opening in the photoresist. Chemical and physical contamination by adjacent materials also are possible.
Quality control techniques for photoresist stencil definition have generally included great care in such things as control of purity, control of exposure, and control of removal of circuit material and stencil material by etching or related techniques. Lift-off techniques have been increasing in favor of removal of stencils after device preparation, because lift-off is significantly gentler than other material removal techniques.
Back-etching for metal removal is a technique which obviates the need to have resist adjacent the device area during cleaning, surface preparation and deposition processes. Back-etching, however, can damage underlying layers in the device because of the over-etching necessary to ensure that the material has been completely removed.
Lift-off stencils and back-etching stencils are known as separate, mutually exclusive techniques, but the prior art does not teach nor suggest the use of a composite back-etch/lift-off technique to achieve a mask opening which has minimal proximity effect to the defined device.
The prior art is typified by the following patents and publications:
U.S. Pat. No. 3,858,304, Leedy et al, "Process for Fabricating Small Geometry Semiconductor Devices," Jan. 7, 1975. Leedy et al shows the use of a resist pattern left temporarily in place to permit lift-off to make very narrow contact metallizations.
U.S. Pat. No. 3,907,620, Abraham et al, "A Process of Forming Metallization Structures on Semiconductor Devices," Sept. 23, 1975, shows the use of a tantalum nitride mask with sputter etching to produce very fine line patterns.
U.S. Pat. No. 3,982,943, Feng et al, "Lift-Off Method of Fabricating Thin Films and a Structure Utilizable as a Lift-Off Mask," Sept. 28, 1976. Feng et al shows a composite photoresist which permits the use of lift-off without sputter etching and results in undercut openings.
U.S. Pat. No. 4,026,742, Fujino, "Plasma Etching Process for Making a Microcircuit Device," May 31, 1977, Fujino shows a contact metallization patterning process using a metal halide treatment to potentiate plasma etching.
U.S. Pat. No. 4,341,850, Coane, "Mask Structure for Forming Semiconductor Devices, Comprising Electron-Sensitive Resist Patterns with Controlled Line Profiles," July 27, 1982. Coane shows a composite photoresist having a semiconductor sandwiched between two resist layers.
R. F. Broom, "Niobium Tunnel Junction Fabrication," IBM Technical Disclosure Bulletin, Vol. 20, No. 5, October 1977, p. 1973. Broom shows a double lift-off technique.
Faris et al, "Josephson Logic Circuit Process Using Edge Junctions, " IBM Technical Disclosure Bulletin, Vol. 25, No. 9, Feb. 1983, pp. 4602-4606. Faris et al shows a multiple resist technique for making Josephson junctions.
The prior art does not provide protection from the proximity effect; the prior art does not teach the use of a composite photoresist technique to minimize proximity effects.